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This article discusses how to create a clock divider in VHDL using the counter method. A clock divider is also known as a frequency divider. I also provide the source code for a simple and configurable clock divider implementation.

A clock divider takes an input clock with a given frequency and produces an output clock with some lower, divided frequency.

Scaling factor

The first thing that needs to be determined is the scaling factor. The scaling factor is simply the ratio of the input clock frequency and the desired output clock frequency. For this article, the scaling factor will be abbreviated as the variable N.

$\frac{Input Clk}{Output Clk} = Scaling Factor (N)$

N represents the number of input clock cycles needed for one output clock cycle. In other words, for every N cycles on the input clock, one cycle on the output clock is generated. Remember that a clock signal is a square wave with a 50% duty cycle. This means that, in one cycle, half of the time is spent high (active) and half of the time is spent low (inactive). Therefore, for a scaling factor of N, the output clock will be set high for N/2 input clock cycles and set low for N/2 input clock cycles.

A clock divider implementation therefore involves using a counter to count to N/2 cycles on the input clock. Once it hits N/2, it toggles the output clock and resets the counter. Note that N must be an even integer in order to have a precise clock divider. If N is not an even integer, you can truncate it to the nearest one and in many cases this will still provide a fairly accurate output.

Clock Divider Source Code

This post discusses the design for a FPGA I2C Slave implementation in VHDL. The final source code for this design can be found in this post here. This I2C Slave implementation provides basic read, write, and addressing functionality. The address of the slave is configurable through a generic. The implementation supports repeated START conditions, but it does not support other "advanced" features such as clock stretching and 10-bit addressing.

The final implementation has been tested on an Altera Cyclone IV FPGA, using a Raspberry Pi 2 as the I2C master.

Learning I2C

This post requires a basic knowledge of the I2C bus. I will not be teaching about or providing a tutorial for I2C here, as there are already many great resources on the internet for learning about it.

The ultimate authority for I2C will always be the specification and user manual. However, this document might be too detailed for those who are only looking for a basic overview. Personally, I recommend any of the following three resources for learning I2C.

• Sparkfun I2C Tutorial.
• Columbia Lecture Presentation.

I2C Slave FSM Design

Below I provide the entire source code for a FPGA I2C Slave implementation in VHDL. To learn more about the implementation's design and FSM, see this post here.

This I2C Slave implementation provides basic read, write, and addressing functionality. It also supports repeated start conditions. The address of the slave is configurable through a generic. Note that this implementation does not currently support "advanced" features such as clock stretching. It also does not support 10-bit addressing, although I'd imagine it wouldn't be too hard to implement this.

This implementation has been tested on an Altera Cyclone IV FPGA. A Raspberry Pi 2 was used as the I2C master.

How to use

The I2C Slave FSM provides the following interface:

tx_done goes high when the I2C Slave module has finished transmitting data to the master. In other words, it signals the completion of a READ command (master reads from slave). The data to be sent to the master must be set in tx_byte.

rx_data_rdy goes high when data is received from the master. In other words, it indicates the completion of a WRITE command (master writes to slave). The received data can be found in rx_byte.

clk is the clock signal for the I2C Slave module itself. This should not be confused with SCL, which is the I2C-bus clock line. For best performance, clk should be significantly faster than SCL.

Source Code

This article discusses how to convert between the common VHDL types. The most common VHDL types are std_logic_vector, signed, unsigned, and integer. The std_logic and std_logic_vector types are defined in the standard logic 1164 package of the IEEE library. This package can be imported as follows:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL

The signed and unsigned types can be found in the numeric_std package. This package can be imported using the code below. The signed type is represented in two's complement form. The source file for the numeric_std package can be found here. For more information on two's complement, check the Wikipedia page.

use ieee.numeric_std.all

VHDL is a strongly-typed language, and does not have automatic type conversion. As a result, converting between different types is often necessary. The libraries above provide type casts and conversion functions between the common VHDL types. These are depicted by the image below.

It is important to note that casting between a std_logic_vector and a signed/unsigned type requires that both signals have the same bit width. Integers do not have a set bit width. Therefore, in the to_signed and to_unsigned conversion functions, note that the first argument is the integer that is being converted and the second argument specifies the bit width of the resulting signed/unsigned type.

It is important to realize that there is no direct conversion between signed and unsigned types. There is also no direct conversion between the std_logic_vector and integer types.

Using these conversions and casts is straightforward. Below is example code illustrating their usage:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

signal stdlvec : std_logic_vector(31 downto 0);
signal unsgn : unsigned(31 downto 0);
signal sgn : signed(31 downto 0);
signal int : integer;

--Conversion from std_logic_vector to signed and unsigned types
unsgn <= unsigned(stdlvec);
sgn <= signed(stdlvec);

--Conversion from signed/unsigned types back to std_logic_vector
stdlvec <= std_logic_vector(unsgn);
stdlvec <= std_logic_vector(sgn);

--Conversion from signed/unsigned types to integer
int <= to_integer(sgn);
int <= to_integer(unsgn);

--Conversion from integer back to 32-bit signed/unsigned types
unsgn <= to_unsigned(int, 32);
sgn <= to_signed(int, 32);